Digital on-chip phase noise measurement
Ouda, Mahmoud; Hegazi, Emad; Ragai, Hany F.;
Abstract
in this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phaselocked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital ΣΔ-frequency discriminator (Σ ΔFD). Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes ©2009 IEEE.
Other data
| Title | Digital on-chip phase noise measurement | Authors | Ouda, Mahmoud; Hegazi, Emad ; Ragai, Hany F. | Keywords | All digital PLL (AD-PLL) | Phase domain | Phase noise | PLL | Sigma delta frequency discriminator (ΣΔFD) | Voltage-controlled oscillator (VCO) | Issue Date | 1-Dec-2009 | Journal | 2009 4th International Design and Test Workshop, IDT 2009 | ISBN | 9781424457489 | DOI | 10.1109/IDT.2009.5404090 | Scopus ID | 2-s2.0-77950427943 |
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